The planned transfer of Navitas GeneSiC technology to Magnachip’s Korean fab puts a timely example behind a much broader engineering question: when a semiconductor process moves, what has to move with it?
For a power or analog product team, the answer is not simply “the same masks and recipe.” The receiving site must reproduce the product’s critical electrical distributions and reliability while rebuilding the controls, models, test limits and release evidence around its own materials and equipment. That is the difference between a process package that has been handed over and a manufacturing route the business can use.
Three things to know
- The invariant is product behavior. Tool settings may change; critical electrical distributions, reliability and product requirements may not.
- The proof is cross-functional. Process control alone cannot establish model accuracy, package robustness, test coverage or route release.
- The release boundary must be named. “Qualified” is incomplete unless it identifies the technology, product, package, customer and manufacturing route covered.
One SiC plan exposes a wider fab-transfer question
On July 23, 2026, Navitas and Magnachip announced a license agreement covering specified GeneSiC silicon-carbide technologies. The companies said the technology is planned to be ported, qualified and internalized at Magnachip’s fab in South Korea. Six days later, Magnachip still described the agreement as a licensing milestone toward its plan.
Status boundary: The agreement is confirmed; the port and qualification are company-stated future work. The public record does not yet establish Magnachip-built production, released part numbers or customer-approved supply.
GeneSiC is a power-discrete example, not an analog-IC transfer template. It matters beyond SiC because every receiving site introduces a new combination of materials, equipment, metrology, controls and ownership. The durable objective is controlled equivalence of the product outcome—not literal duplication of every local recipe.
First, define which job is actually moving
“Process port” can hide three different programs. A technology-platform transfer establishes a designable, controlled process at another site. An existing-product transfer adds the die, wafer-sort, assembly and final-test route for particular part numbers. A design migration adapts a circuit into another process or PDK and may require layout, IP and verification changes.
These jobs overlap, but they do not carry the same proof burden. A platform can be qualified before any customer’s product is released. A product can ship from two sites without being interchangeable in every application. A PDK can pass design checks without proving that its models predict the receiving fab’s silicon.
Before the first comparison lot, write the transfer object in one sentence: exact technology revision, product or design database, intended fab/assembly/test route, market scope and approval decision. Without that sentence, teams can complete different tasks and still use the same word—“qualified.”
Separate what must remain invariant from what may change
The product specification, device and layout intent, critical electrical distributions, relevant failure mechanisms, traceability and release criteria form the controlled reference. The mask database, process specification, PDK/model set, test program, reliability plan, deviations and owners must be versioned with it.
Qualified material sources, tool chambers, recipe setpoints, sampling plans and local control limits may be adapted at the receiving fab. Every adaptation, however, needs an evidence owner and acceptance criterion. Same recipe is neither always possible nor the real acceptance criterion; controlled product behavior is.
The following Portability Matrix is a ChinaSemiOps engineering framework, not a disclosed Navitas or Magnachip workflow.
1. Controlled baseline
- Keep invariant: product requirements, device/layout intent, revision identity and acceptance criteria.
- May adapt: local instructions and the responsibility split.
- Evidence: released transfer manifest, configuration cross-reference, approved deltas and named owners.
2. Manufacturing behavior
- Keep invariant: critical structures and process-output distributions.
- May adapt: qualified materials, equipment, recipes, metrology sampling and control limits.
- Evidence: measurement correlation, process-window data, inline distributions, repeated wafers/lots and an excursion plan.
3. Electrical predictability
- Keep invariant: required device behavior, corners, matching, parasitics and safe operating boundaries.
- May adapt: model extraction details and local monitor/test implementation.
- Evidence: wafer maps and lot distributions, model-to-silicon residuals, representative circuit correlation and guard-band rationale.
4. Product robustness
- Keep invariant: mission-profile reliability, protection behavior, package interaction and final product limits.
- May adapt: assembly route, stress implementation and production-test flow when the deltas are qualified.
- Evidence: failure-mechanism-based reliability, package/assembly data, test correlation, coverage and limit setting.
5. Released route
- Keep invariant: traceable product identity and approved quality/customer scope.
- May adapt: local records, ramp controls and capacity plan.
- Evidence: qualification boundary, production-control readiness, change notification, genealogy and exact product/customer release.
Public foundry quality systems illustrate why these layers belong together. X-FAB, for example, lists in-process inspection, SPC, PCM, WAT, outgoing inspection, reliability monitoring and traceable process-change management. GlobalFoundries describes a PDK as models, rules and libraries, including DRC, LVS and ESD checks. Neither a control plan nor a PDK alone proves a released product route.
The framework stays; the technical proof changes
For SiC power devices, substrate and epitaxy controls, crystalline defectivity, gate-oxide behavior, edge termination, ruggedness and high-current package interaction may dominate. Which stresses matter depends on the device and mission profile; a generic SiC checklist is not enough.
For BCD, SOI and high-voltage CMOS ICs, the receiving route must also preserve isolation behavior, high-voltage device characteristics, latch-up/ESD paths, safe operating area, passive accuracy, parasitics and model corners. Precision and mixed-signal products add matching, offset, noise, drift, trim range, NVM options and production-test guard bands. Our earlier guide to SOI, BCD and high-voltage analog process choice shows why defining that process envelope early matters.
X-FAB’s public description of moving its XH018 high-voltage CMOS platform from Malaysia to France is a useful non-SiC example: the announced receiving route included a PDK and supporting IP, not only a wafer recipe. The published page does not reveal its cross-site distributions or product-by-product customer approvals, so it should be read as a vendor-stated availability example—not a universal qualification recipe.
The five review layers generalize. The critical parameters, failure mechanisms, models, test coverage and acceptance limits do not. AEC likewise keeps qualification frameworks for integrated circuits and discrete semiconductors separate; component qualification also remains distinct from a customer’s application approval.
Put a maturity verb and an owner beside every commitment
Use four working verbs: defined, correlated, qualified, released. Then add the object. “Model set correlated to receiving-fab silicon” is actionable. “Process qualified” is not, unless everyone knows whether it means a process module, technology platform, package, product, customer or application.
At the next port review, give each matrix layer a current verb, next evidence item, acceptance owner and decision date. This small discipline exposes whether a schedule is waiting on a measurement system, a distribution study, model update, reliability delta, test correlation or customer release.
A power or analog process is portable when site-specific manufacturing can preserve the product’s required behavior and the team has correlated the models, reliability, test and release controls for the exact route being approved. Not when every recipe matches—and not when the transfer agreement is announced.
Planning a non-confidential GDS or design handoff for a power or analog fab route? ChinaSemiOps can help define the design-deliverable and manufacturing-interface questions before scope is frozen.
Disclosure: The Navitas–Magnachip example is based on public company information. The Portability Matrix is a general ChinaSemiOps engineering framework, not a description or assessment of either company’s confidential transfer plan. The featured photograph is an illustrative NIST cleanroom image and is not associated with either company.