Design targets

Power-stage configuration

Three integrated half-bridges

Power-stage voltage class

60 V; supply headroom and transients require evaluation

Logic supply

4.5–5.5 V (5 V nominal)

Continuous output current

8 A at 25 °C case temperature, subject to thermal limits

Peak output current

15 A class; pulse duration, duty cycle and thermal limits require validation

Control inputs

Six external pulse-width modulation (PWM) commands

Pin compatibility

44-pin signal-assignment compatibility target

Case-temperature range

−40 to +125 °C

Practical operating notes

• Design is complete and pre-silicon. The listed specifications are design targets, not measured results. The 8 A continuous target assumes a 25 °C case; cooling, duty cycle and shared-package dissipation constrain operation. The 15 A peak-class target requires pulse and thermal validation.
• The 60 V class does not establish safe operation on every 60 V supply rail. Evaluate voltage headroom, transients and undervoltage behavior. Controller signals must meet the logic-input thresholds.
• An external controller supplies the PWM commands and motor commutation. System design must address inductive-energy paths, regeneration, supply bypassing and any required external diodes.
• Current sensing covers forward current through the upper power transistors only; it does not measure all phase-current paths. Cycle-by-cycle limiting disables all three outputs when a sensed phase crosses the threshold. Input-edge reset behavior and the current-limit disable input require controller-level review.
• Short-circuit and temperature outputs provide warnings rather than automatic shutdown. The controller or external circuitry must implement the required response.
• Matching the 44-pin signal assignments is a compatibility target. Package variant, mechanical fit, thermal and electrical behavior, and board-level operation still require validation before interchangeability can be established.