How an EV traction pack connects safely to its inverter and lets go when something fails: precharge, contactors, fuses, pyro disconnects, drivers and the energy that remains afterwards.
EV Traction-Battery Protection: Precharge, Contactors, and Fault Disconnect Read More »
A battery-storage inverter design decision, and why a peak-efficiency headline is only the start: what hybrid SiC modules contain, where efficiency boundaries sit, and which evidence to request from suppliers.
Hybrid Silicon–SiC Modules for Battery Storage: What Efficiency Headlines Leave Out Read More »
How to plan an analog IC production handoff: what wafer test and final test each cover, why trim stage and package stress matter, and a proposed checklist for evidence, owners and release decisions.
From Wafer Test to Final Test: Planning an Analog IC Production Handoff Read More »
NVIDIA publicly names Navitas in its 800 VDC AI data center power ecosystem, and Navitas has demonstrated relevant GaN power hardware. But the public record does not yet prove a disclosed production socket inside an NVIDIA AI server package. The difference matters for power semiconductor strategy.
Navitas, NVIDIA, and 800 VDC: What the Public Evidence Actually Shows Read More »
A factual guide to the universal pricing logic used by semiconductor foundries. This post decodes the industry-standard cost structures for MPW (grid-based seat allocation) and Full-Mask NTO (layer-proportional NRE), providing the essential formulas for PMs and engineers before requesting a quote
Industry Standard Pricing Structure: MPW and Full-Mask (NTO) Read More »
Global standards like WAT and SBL exist everywhere, but in China, they operate under different pressures: speed, scale, and localization. Here is how to align your engineering expectations with the reality of Chinese mass production.
Beyond the Standard: 3 Operational Milestones in China Fabs Read More »