Design targets

Gate-drive configuration

Four outputs for an external N-channel MOSFET full bridge

Switch-node voltage class

80 V; temperature-dependent voltage margin and transients require evaluation

Driver bias supplies

9.5–15 V; both supply pins at the same potential, with startup margin required

Peak gate-current targets

2.6 A pull-up and 2.4 A pull-down, based on reference typical test conditions

Control interface

Input comparator, high-side enable and overall disable

Turn-on delay control

Separately resistor-set high-side and low-side delays

Pin compatibility

Pin-assignment compatibility objective; final package selection deferred

Practical operating notes

• Design is complete and pre-silicon. The listed figures are design targets, not measured results. The peak gate-current targets use reference typical values at 12 V bias and 25 °C: pull-up with the output at 0 V, pull-down with the output at 12 V. These are momentary gate currents, not motor-load currents or guaranteed minimum values.
• The 80 V switch-node class is not an unrestricted bus-voltage rating across all temperatures. Cold-temperature limits, switching transients and voltage headroom require validation. Driver startup also depends on undervoltage thresholds and bias-supply margin.
• The comparator controls bridge switching; an external controller and suitable feedback circuitry must provide the required system behavior. Check comparator input range, logic thresholds, source-node movement and external MOSFET timing when setting the two turn-on delays.
• The high-side enable input can hold both high-side gates off. Overall disable holds all four gate outputs low. These functions do not establish complete system fault protection or unconditional prevention of simultaneous conduction.
• High-side bias uses a charge-pump-assisted bootstrap arrangement with external diodes and capacitors. Startup, refresh, gate charge, leakage and duty cycle must be evaluated before extended high-side on-time can be supported.
• Package selection remains open. Pin assignments, mechanical fit, thermal behavior, electrical timing and board-level operation require validation before interchangeability can be established. External power transistors, current sensing, inductive-energy paths and fault response remain system-design responsibilities.